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Call:9871280005

Verilog Training in Faridabad/ Gurgaon/ Delhi/ Noida

  • Street: faridabad
  • City: Faridabad
  • State: Haryana
  • Country: India
  • Zip/Postal Code: 121008
  • Listed: April 12, 2016 6:43 am
  • Expires: 4603 days, 12 hours
Verilog Training in Faridabad/ Gurgaon/ Delhi/ Noida

Description

Verilog Training in Faridabad/ Gurgaon/ Delhi/ Noida

Topics to be covered:

Module 1: Introduction

  • Introduction to VLSI & CAD tools
  • VLSI Design flow
  • Verilog History
  • Why HDL needed
  • HDL vs. Programming Languages

Module 2: Lexical conventions

  • Lexical Tokens
  • White space
  • Comments
  • Numbers
  • Identifiers
  • Attributes

Module 3: Data types

  • Value set
  • Net and Variables
  • Vectors
  • Strengths
  • Implicit Declarations
  • Net types
  • Regs
  • Integers, reals, times, and real times
  • Arrays
  • Parameters

Module 4: Modeling styles and Gate Level Modeling

  • Design approaches – top down and bottom up
  • Gate primitives and Gate instantiation
  • Module instantiation

Module 3: Test Bench Writing

  • Introduction
  • Steps for writing a test bench

Module 5: Data Flow Modeling and Operators

  • Continuous assignment – assign keyword
  • Operators, their precedence and the expressions

Module 6: Delays Modeling (timing control)

  • inertial delays
  • transport delays
  • mixed (inertial and transport) delays
  • rise, fall, turnoff delays
  • min, typ, max delays
  • wire, gate, distributed, lumped delays
  • specify block and pin to pin (propagation) delays
  • state dependent path or conditional, edge sensitive path delays

Module 7: Behavioral Modeling

  • Behavioral Model Overview
  • Procedural Assignments
  • Conditional statement
  • Case statement
  • Procedural timing control
  • Block statements

Module 8: Advanced Verilog

  • assign de-assign
  • force release
  • events
  • compiler directives
  • system tasks
  • timing checks
  • file I/O

Module 9: Task and Functions

  • Distinction between the task and Function
  • Functions
  • Tasks

Module 10: FSM – Verilog Coding

  • FSM – An Introduction
  • Mealy and Moore FSM
  • State Memory
  • State Diagrams and State table
  • Verilog implementation of Mealy FSM
  • Verilog implementation of Moore FSM

Exam

Minor Project

Eligibility : B.Tech (ECE) – 2nd, 3rd, and 4th year student

Fees : Rs. 6,000/-

Training Schedule:- Weekends: Saturday Sunday
Morning & Evening batches both are available. Training schedule will be based on the availability of the trainer or tutor and strength of group.

Venue of Classes : Faridabad (Home tutions are also available depending on the number of availability of students.

Duration: 30 hours + project

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