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VHDL Basic Training in Faridabad/ Gurgaon/ Delhi/ Noida

  • Street: faridabad
  • City: Faridabad
  • State: Haryana
  • Country: India
  • Zip/Postal Code: 121008
  • Listed: April 12, 2016 7:06 am
  • Expires: 3862 days, 13 hours
VHDL Basic Training in Faridabad/ Gurgaon/ Delhi/ Noida


VHDL Basic Training in Faridabad/Gurgaon/ Delhi/Noida

Topics to be covered:

Module 1: Introduction :

Introduction to VLSI, Design Styles, ASIC vs. SOC vs. FPGA, Design flow and tool, Why HDL needed, What is VHDL, VHDL History, HDL vs. Programming Languages, Questions

Module 2: Getting Started:

Basic Terminology ─ Entity, Architecture, Configuration, Package, Identifiers- The Basic Identifiers, The Extended Identifiers, The source files and libraries, The ‘Use’ Clause , The compilation procedure , Questions

Module 3:

The Design: Entities and the Syntax: Signals list and Ports & Types: Std_logic , Architecture Body and the Syntax, Statement and the Classification, Questions

Module 4: The Language Elements I:

  •  Data Objects: Constants, Variables, Signals
  •  Operators : Miscellaneous, Multiplication, Addition, Shift, Relational, Logical
  •  Questions

Module 5: Dataflow Style of Modelling

  • Introduction
  • Using Simple assignment Statement
  • Using Selected assignment Statement
  • Using Conditional assignment Statement
  • Delta Delay
  • Multiple Drivers
  • Labs

Module 6: Structural Style of Modelling

  • Introduction
  • Modelling Template
  • Component Declaration
  • Component Instantiation Statements
  • 4 x 1 Mux Example
  • Resolving Signal Values
  • Labs

Module 7: Test bench Writing

  • Introduction
  • The Test bench-Entity
  • The Test bench-Architecture : Signal Declaration, Design Under Test (DUT) Instantiation, Stimulus Generation, Output Monitoring
  • Labs

Module 8: The Language Elements II

  • Data Types: Pre-defined Types, Enumeration Types, Integer Types, Floating Point Types, Physical Types, Array, Records, Access Types
  • Exercise

Module 9: Behavioral Style of Modelling

  • The Processes Statement
  • Sensitivity list
  • Concurrent versus Sequential Signal Assignment
  • Variable Assignment versus Assignment
  • IF Statement
  • Case Statement
  • Loop Statement
  • Sensitivity list versus Wait Statement
  • Wait Statement
  • Delays: Inertial delay, Transport delay
  • Labs

Module 10: FPGA Design Flow

  • Simulation
  • Synthesis
  • Place-and-Route
  • Device programming
  • Labs & Project


Eligibility : B.Tech (ECE/CSE)

Fees : Rs. 8,000/-

Training Schedule:
Weekends: Saturday Sunday
Morning & Evening batches both are available. Training schedule will be based on the availability of the trainer or tutor and strength of group.

Venue of Classes : Faridabad (Home tutions are also available depending on the number of availability of students.

Duration: 40 hours + project

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